The present invention relates to a transmission of the network-on-chip architecture. More particularly, the present invention relates to a method for dynamical adjusting channel direction and the network-on-chip architecture thereof.
Please refer to FIG. 7, it is a schematic diagram of conventional network-on-chip architecture of the mesh topology. In FIG. 7, the network-on-chip architecture 700 is exampled as 4×4 architecture. The network-on-chip architecture 700 comprises sixteen routers 702 and sixteen processing elements 704. Wherein, every processing element 704 is connected to the corresponding router 702 through the network interface 706. Every router 702 has four direction channels for connecting to the peripheral routers 702.
Please refer to FIG. 8, it is a schematic diagram of circuit block of conventional single router. The router 702 comprises an interleaver 828, five registers 822a˜e, five multiplexers 824 a˜e, five control logic circuits 826 a˜e, four direction channels (labeled as 802˜816), and a plurality of channels connected to the processing element 704 of FIG. 7 (labeled as 818 and 820).
In the prior art, the multiplexers 824 a˜e and the interleavers 828 are controlled by the control logic circuits 826 a˜e. The registers 822a˜e are respectively connected between the corresponding control logic circuits 826a˜e and the input channels 804,808,812,816,820. The network interface 706 of the router 702 is connected to the network interface 706 of the processing element 704 for communicating through the input channel 820 and the output channel 818 connected to the processing element 704. Wherein, the network interface 706 is connected to the multiplexer 824a and the register 822a. 
The output channel 802 of the west direction channel is connected to the multiplexer 824b, and the input channel 804 is connected to the register 822b. The output channel 806 of the east direction channel is connected to the multiplexer 824c, and the input channel 808 is connected to the register 822c. The output channel 810 of the south direction channel is connected to the multiplexer 824d, and the input channel 812 is connected to the register 822d. The output channel 814 of the west direction channel is connected to the multiplexer 824e, and the input channel 816 is connected to the register 822e. 
In FIG. 8, when the router 702 outputs the data to another router 702 through the output channel 802 of the west direction channel, only the output channel 802 is used for transmission due to the transmission directions of the output channel 802 and the input channel 804 are fixed. The input channel 804 is at standby state if no data is transmitted from another router 702. Under this channel disposition, if the amount of the transmission data is very large, the input channel 804 is still at the standby state, and only the output channel 802 is used to transmit. Thus, the transmission time of the data is very long, and the output channel 802 is occupied. If another data reaches the router continuously, another data is transmitted after the present data have been transmitted. Therefore, the conventional network-on-chip architecture will cause large waste of time and source.